1. Field of the Invention
The present invention relates to data converters, and, more particularly, to a successive-approximation-register (SAR) analog-to-digital converter (ADC) and method.
2. Description of Related Art
Data converters, such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are used for converting data between analog signals and digital signals. ADCs convert analog signals to digital signals. Various types of ADCs exist, such as delta-sigma modulator ADCs or successive-approximation-register (SAR) ADCs.
With reference now to FIG. 1, a block diagram of an exemplary N-bit SAR ADC 100 according to the prior art is shown in which N is an integer greater than one. SAR ADC 100 includes an N-bit digital-to-analog converter (DAC) 102, an N-bit register 104, and a SAR logic block 106 coupled together as shown in FIG. 1. N-bit DAC 102 includes an R-2R ladder network of resistors R and 2R in order to convert digital signals to analog signals. SAR ADC 100 also has a comparator 108. Comparator 108 receives as one of its input an analog input voltage VIN of an analog input signal received by SAR ADC 100 and further receives as another one of its input a DAC voltage VDAC from N-bit DAC 102. The output of comparator 108 is fed back into SAR logic block 106 as shown in FIG. 1. The converted digital output signal DIGITAL DATA OUT is output from N-bit register 104.
Additionally, each bit of N-bit DAC 102 and N-bit register 104 is coupled to either a high reference voltage VR+ or low reference voltage VR− through a respective switch s1, . . . , sm, sn as shown in FIG. 1. For example, if the most significant bits (MSBs) of N-bit DAC 102 and N-bit register 104 are to be set to a high value, then the respective switch s1 switches to couple both MSBs to the reference voltage VR+. On the other hand, if the MSBs are to be set to a low value, then the respective switch s1 switches to couple both MSBs to the reference voltage VR−.
A SAR ADC implements a binary search algorithm for successively approximating the analog input value as a digital output value. Referring now to FIG. 2, a flow chart of an exemplary search algorithm 200 for SAR ADC 100 according to the prior art is shown. Search algorithm 200 starts at block 202 and moves onto block 204, which depicts a bit count BC being initialized and set equal to an Nth bit value and reflects the bit count BC being set to the most significant bit (MSB). Following block 204, block 206 illustrates DAC voltage VDAC being initialized to a mid-scale voltage value by setting the SC bit (e.g., MSB) to the high reference voltage VR+ and all remaining bits of N-bit DAC 102 and N-bit register 104 to the low reference voltage VR−.
Search algorithm 200 then proceeds to block 208, which depicts BC BIT (e.g., the Nth bit or MSB at this time) of N-bit DAC 102 and N-bit register 104 being set equal to the high reference voltage VR+. Following block 208, decision block 210 shows a comparison being made between analog input voltage VIN and DAC voltage VDAC. If analog input voltage VIN is greater than DAC voltage VDAC, then search algorithm 200 next moves to block 212, which shows BC BIT of N-bit DAC 102 and N-bit register 104 being maintained equal to the high reference voltage VR+. Search algorithm 200 then proceeds to block 216. On the other hand, if, at decision block 210, analog input voltage VIN is not greater than DAC voltage VDAC, then search algorithm 200 proceeds to block 214. Block 214 depicts that BC BIT of N-bit DAC 102 and N-bit register 104 being changed to the low reference voltage VR−.
Search algorithm 200 then proceeds to block 216. Block 216 represents the moving to the next bit of N-bit DAC 102 and N-bit register 104 by setting the next value of bit count BC equal to the current bit count BC minus one (1). Following block 216, decision block 218 illustrates a determination whether bit count BC equals zero (0). If bit count BC does not equal zero (0), then search algorithm 200 loops back before block 208 and sets this next BC BIT to the high reference voltage VR+ and continues therefrom. On the other hand, if bit count BC does equal zero (0), then search algorithm 200 ends at block 220.
As an example, if N-bit SAR ADC 100 is a 4-bit SAR ADC (e.g. N=4), then the bit levels for a 4-bit SAR ADC are from 0 to 15. In this example, the voltage VIN equates to a level value of 9.5. The bit count BC is set equal to four (4) at block 204. Also, for this example, a one (1) value is representative of the high reference voltage VR+, and a zero (0) value is representative of the low reference voltage VR−. The voltage VDAC starts at the mid-scale voltage value by setting the bits of N-bit DAC 102 and N-bit register 104 to the value 1000 (e.g., equal to 8) at block 206. Again, BC BIT is set to the one value (e.g., the high reference voltage VR+).
The voltage VIN equal to 9.5 is compared with the voltage VDAC equal to 8. Since 9.5>8 at decision block 210, the BC BIT (e.g., fourth bit) is maintained as one and the voltage VDAC is maintained as 8 at block 212. At block 216, BC is set equal to three (3) (4−1). Since BC is not equal to zero at decision block 218, the new BC BIT (e.g., third bit) is set equal to one at block 208. The voltage VDAC is now equal to 12 (e.g., bits of N-bit DAC 102 and N-bit register 104 are 1100). Since 9.5<12 at decision block 210, the BC BIT (e.g., third bit) is changed back to zero at block 214. BC is then set to 2 (e.g., 3−1) at block 216. Since BC is still not equal to zero at decision block 218, the next BC BIT (e.g., second bit) is set equal to one at block 208.
The voltage VDAC is now equal to 10 (e.g., bits of N-bit DAC 102 and N-bit register 104 are 1010). Since 9.5<10 at decision block 210, the BC BIT (e.g., second bit) is changed back to zero at block 214. BC is then set to 1 (e.g., 2−1) at block 216. Since BC is not equal to zero at decision block 218, the next BC BIT (e.g., first bit) is set equal to one at block 208. Since 9.5>9 at decision block 210, the BC BIT (e.g., first bit) is maintained as one at block 212. BC is then set equal to zero at block 216. Since now BC equals zero at decision block 218, search algorithm 200 ends at block 220.
As illustrated, the above search algorithm requires going through each bit by setting them to a one value and testing to see whether the voltage VIN is greater than the voltage VDAC. If so, then the one value for the bit is kept. However, if the voltage VIN is not greater than the voltage VDAC, then the bit has to be changed back to the zero value. Thus, at times, the voltage values for the bits of the DAC need to be changed back and forth to successively approximate and end up at the desired voltage VDAC.
Thus, search algorithm 200 requires a number of changes to the bits in order to finally reach the right value. For each pass of the operational loop through search algorithm 200, an initialization and setting of a bit value and then possibly another change to the bit value may be performed.
The present invention recognizes the desire and need for a more efficient search algorithm for a successive-approximation-register (SAR) analog-to-digital converter (ADC), which would reduce the number of changes having to be made to the element values. The present invention recognizes the desire and need for reducing the number of steps and operations performed by the search algorithm for the SAR ADC and the number of passes made through the search algorithm loop. The present invention overcomes the problems and disadvantages that have been encountered with the prior art.